Apple designs electronic devices, operating systems and digital services including iPhone, Mac and App Store.
Experienced GPU Electrical Analysis Engineer
Au sein de Silicon Technologies chez Apple, l’ingénieur en analyse électrique GPU contribue à la conception de GPU performants et économes en énergie. Il pilote l’analyse électrique, de la planification à la clôture de conception, et collabore avec les équipes de conception physique sur l’intégrité de l’alimentation, les réseaux de distribution électrique et l’intégration des puces. Le poste est indiqué à Cambridge et à Londres.
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The full description published by Apple.
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU. You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices.
Together, you and your team will enable our customers to do all the things they love with their devices. This exciting role requires a mix of strategic engineering along with hands-on, technical work. You'll be responsible for realizing the complete electrical analysis closure from early design planning to tapeout. You will have hands on experience in physical design and large chip integration. Join us! As a GPU Electrical Analysis engineer, you will work closely with the Physical
Design team to design power grid specification that achieves the best balance between power integrity targets and PNR performance, power and Area (PPA). You will be involved with the definition of on-die power switch topology, wake-up schemes, and in-rush control. Collaboration with internal teams to drive bump map, custom RDL routing, and package design/optimization will be required. You will develop test structures, procedures/automation, and analysis methodologies for electrical analysis challenges.
You will perform Power Integrity, EM, and ESD analysis, drive feedback, and recommend design solutions. Finally, you will communicate and drive the needs of PD and Electrical Analysis with cross-functional teams that will enable achieving the goals of the back-end design for the project. Experience planning, implementing, and analyzing power delivery networks. Experience designing and analyzing power delivery schemes with power switches. Experience with Signal/Power Integrity checks including Electromigration, Static IR and Dynamic Voltage drop checks.
Experience with global power integrity tool (e.g. Redhawk, Voltus). Minimum of BS/MS in EE + years of relevant experience. Experience with on-die high frequency power delivery, and exposure to off-die concepts and models. Experience with bump planning and redistribution layer routing strategies, including methods for working with IO bumps and edge encroachment scenarios. Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
Background with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative technologies. Track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class GPU designs. Circuit design and simulation background a plus, but not required. Experience with global timing verification, SPICE simulation/analysis, and Physical
Design Verification Flows.
Requirements
- Expérience en planification et analyse de réseaux de distribution électrique
- Expérience en conception de schémas d’alimentation avec commutateurs de puissance
- Expérience en vérifications d’intégrité du signal et de l’alimentation, notamment électromigration et chutes de tension
- Expérience avec les outils d’intégrité de puissance Redhawk ou Voltus
- Diplôme minimum BS/MS en génie électrique
- Expérience en alimentation électrique haute fréquence sur puce
- Expérience en planification des bumps et stratégies de routage des couches de redistribution
- Connaissance de l’intégration ASIC, notamment floorplanning, distribution d’horloge et d’alimentation et intégration d’I
- Expérience de conceptions SoC de grande taille (>20M portes) à des fréquences supérieures à 1 GHz
- Expérience en vérification temporelle globale, simulation/analyse SPICE et flux de vérification de conception physique
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