Apple designs electronic devices, operating systems and digital services including iPhone, Mac and App Store.
Front-End Implementation (Synthesis) Engineer
Apple is recruiting a Front-End Implementation engineer to join the GPU Front End Implementation team in London. The role involves optimising the PPA of netlists, meeting quality milestones and collaborating with the RTL and Physical Design teams. A licence or bachelor’s degree in electrical engineering and proficiency in Verilog or SystemVerilog and scripting languages are required.
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The full description published by Apple.
Imagine working in a team where the only limits are the laws of physics and your imagination. At Apple, phenomenal ideas have a way of becoming phenomenal products and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The same real passion for innovation that goes into our products also applies to our practices. Join the team that optimises and delivers world class GPUs into Apple Silicon.
As part of the GPU Front End Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day. Join us! Candidates will be responsible for PPA optimisation of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the outstanding GPUs for the best consumer products.
If you’re ready to help chart the future of Apple Silicon, we would love to talk to you. Minimum of BSc in EE. Proficient in Verilog and/or System Verilog and scripting languages. Experience with physical synthesis, including logic and PPA optimisation techniques. Understanding and application of physical design and static timing analysis principles. Familiarity with DFT insertion. Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level. Experience implementing ECO's for functionality and timing.
Ability to analyze critical paths and guide RTL designs to efficient solutions. Experience using logic equivalence tools for RTL and Gate-level designs.
Collaborate optimally with IP teams spanning multiple sites.
Requirements
- PPA optimisation of the netlist
- Experience with physical synthesis
- Understanding and application of physical design principles
- Understanding and application of static timing analysis principles
- Experience implementing ECOs for functionality and timing
- Ability to analyse critical paths
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